The availability of high speed integrated circuit chips has resulted in a need for suitable interconnection technology that offers high wiring density, good electrical characteristics for the propagation of high speed signals, and good thermal performance. Multilayer interconnection systems with fine line conductors and associated ground planes have been proposed for applications in high performance systems. C. W. Ho et al., IBM J. Res. Dev., 26: 286-296 (May 1982), and C. W. Ho et al., VLSI Electronics: Microstructure Science, 5(3): 103-143 (Academic, New York, 1982). Fine geometry copper conductor lines defined in a photolithographically patterned layer of a low-dielectric constant polymer, such as a polyimide, have emerged as a versatile packaging approach for the conductive interconnection lines between densely packed integrated circuit chips in high performance systems.
The customary approach to fabricating interconnect structures uses copper conductor lines that are several microns thick. The metal is deposited using a thin-film technique and is subsequently patterned using a resist mask. A wafer substrate with the patterned conductor lines is then spin-coated with a dielectric (e.g., polyimide). Planarity of the overall layer, which is of crucial importance for good performance and manufacturing yield, is poor unless one employs multiple coats of the dielectric film. The process is tedious and due to the presence of thick dielectric films, the interconnect structures are subjected to high levels of stress, resulting in poor yields and lowered reliability.
An alternative approach, which circumvents the limitations of the customary approach, uses photosensitive polyimide as the dielectric. In this approach, the polyimide film is photopatterned to create trenches into which the copper conductor lines are electroplated to a height equal to the polyimide film thickness, thus assuring near perfect planarity of all the individual signal layers. See K. K. Chakravorty, Proc. of Elect. Comp. Conf., 135-142 (1988); and Chakravorty et al., Proc. 3rd Int. SAMPLE Elec. Conf., 3: 1213-1223 (1988).
In general, the alternative approach utilizes the following steps to produce conductive features having fine geometry: (1) depositing a thin layer of a metallic seed layer on a dielectric substrate, (2) patterning the seed layer to form fine geometry lines that serve as the electroplating base for the conductor lines, (3) spin-coating a layer of a photosensitive dielectric (e.g., photosensitive polyimide) over the dielectric substrate and patterned seed layer, (4) photolithographically patterning the layer of the photosensitive dielectric to form dielectric features (defined by trenches) having fine geometry, and also uncovering the seed layer between the dielectric features, and (5) electroplating an electrically conductive material between the patterned dielectric features onto the metallic seed layers to form electrically conductive features.
The alternative approach requires the presence of an electroplating seed layer in the polyimide trenches, which needs to be electrically connected to the cathode of the electroplating bath during step (5), described above. A typical multichip module substrate may use a design such that it is not possible to extend every interconnection line to the edge of the module so as to electrically connect it to the cathode of the electroplating bath. In order to make this alternative approach work under such conditions, a technique is required whereby the "isolated" lines may be electrically connected to the edge and, thus, the cathode of the bath during the electroplating step. Upon completion of the plating process, the electrical connection may then be severed, restoring the electrical isolation of the conductor lines. This approach can be used for every signal layer in a multilayer high-density interconnect structure.
There are several ways of forming these temporary electrical connections to the outer edge of the substrate so that electroplating of "isolated" lines can be done. One such method is given in U.S. Pat. No. 4,661,214. This method requires the presence of conductive "islands" under the polyimide which are initially conductive and they are rendered resistive by a temperature treatment step. One drawback of such an approach is that the material system is based on silver (Ag) in contact with a chalcogenide film. Control of the stoichiometry of the film is often difficult and affects the temperature of disconnection. The material system may generate by-products during the baking process which may adversely affect the reliability of the copper-based interconnect structures by leading to corrosion. Another drawback is the poor adhesion of silver to the substrate material (silicon, etc.). In the present approach, this electrical connection is achieved by a blanket sputtered layer of Ta metal. Since any conductive metal used for such a process during the electroplating step will get copper deposited on it, it is necessary to cover its surface by an insulating layer to prevent this from happening. However, if a thin layer of an electrically conductive material is utilized to connect such features to the edge, complete and even coverage of its upper surface with an insulating layer, including edge coverage, is hard to achieve. This insulating layer is necessary so that there is no plating taking place except in the previously photodefined dielectric trenches with the plating base seed layers at their bottom. If the overlying electrically insulating film contains microscopic defects or weak spots, these will cause substantial problems during the electroplating step, such as unwanted electroplating and nodule formation, resulting in an unsatisfactory conductive line. Another problem that needs to be addressed is that of preventing the metal lines that are in contact with the photosensitive dielectric, especially a polyimide, from being corroded by moisture and ionic contaminants present in the dielectric. Yet another problem that needs to be addressed is that of poor adhesion between electroplated metal lines and the dielectric, at their interfaces.